A high-performance CMOS 70-MHz palette/DAC

Author

Letham, Lawrence ; Ahuja, Bhupendra K. ; Quader, Khandker N. ; Mayer, Ronald J. ; Larsen, Robert E. ; Canepa, George R.

Volume

22

Issue

6

fYear

1987

fDate

12/1/1987 12:00:00 AM

Firstpage

1041

Lastpage

1047

Abstract

A VLSI circuit has been developed that combines dual-ported RAMs and three high-speed 8-b digital-to-analog converters (DACs). It is known as a palette/DAC. A 6-2 segmented DAC architecture improves differential linearity and monotonicity. The current-source cell uses a cascode device to improve the DAC´s linearity. A reference current, set by an on-chip bandgap reference voltage generator, and its associated distribution scheme eliminate the negative effects of threshold mismatches between current source cells, supply line resistance, and noise. The maximum conversion rate is 70 MHz with typical DC differential nonlinearity of 0.48 LSB (least significant bit). The 253-mil/SUP 2/ is designed on a double-metal CMOS process and consumes 1.2 W of power.

Keywords

CMOS integrated circuits; Computer graphic equipment; Digital integrated circuits; Digital-analogue conversion; Random-access storage; VLSI; computer graphic equipment; digital integrated circuits; digital-analogue conversion; random-access storage; Buffer storage; Circuits; Color; Current supplies; Graphics; Linearity; Monitoring; Read-write memory; Switches; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1987.1052853

Filename

1052853