A multiple-access pipeline architecture for digital signal processing

The design of a special-purpose CMOS processor for digital signal processing is described. A high degree of processing concurrency is achieved through the use of two modified pipelined architectures in parallel. Each pipeline section is connected to a bus for maximum flexibility in accessing any stage in the pipeline. Each pipeline section can be dynamically configured under microprogram control to perform different function evaluations. One pipeline processes the mantissa part of the data, while the other pipeline processes the exponent part. In this fashion, different operations could be run concurrently on the different fields of the floating-point data. Integer and fixed-point data can be processed by the arithmetic logic unit (ALU) under microprogram control. Pipeline latency and stage utilization for certain mathematical operations are discussed. An ALU was designed using this architecture in CMOS technology. The ALU is microprogram-controlled to perform complex-number floating-point multiplication in 520 ns, and complex-number floating-point addition in 240 ns with a power requirement of 250 mW when operating at 25 MHz (5-V supply)