Title :
Integrated injection logic: a new approach to LSI
Author :
Hart, Kees ; Slob, Arie
fDate :
10/1/1972 12:00:00 AM
Abstract :
Multicollector transistors fed by carrier injection are used. A simplified (five masks) standard bipolar process is used resulting in a packing density of 400 gates/mm/SUP 2/ with interconnection widths and spacings of 5 μm. The power-delay time product is 0.4 pJ per gate. An additional advantage is a very low supply voltage (less than 1 V). This, combined with the possibility of choosing the current level within several decades enables use in very low-power applications. With a normal seven-mask technology, analog circuitry has been combined with integrated injection logic (I/SUP 2/L).
Keywords :
Digital integrated circuits; Large scale integration; Logic circuits; Logic gates; digital integrated circuits; large scale integration; logic circuits; logic gates; Chip scale packaging; Circuit testing; Delay; Diodes; Electron devices; Fabrication; Immunity testing; Large scale integration; Logic circuits; Manufacturing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1972.1052891
