DocumentCode :
904762
Title :
Testing Resistive Opens and Bridging Faults Through Pulse Propagation
Author :
Favalli, Michele ; Metra, Cecilia
Author_Institution :
Dept. of Eng., Univ. of Ferrara, Ferrara
Volume :
28
Issue :
6
fYear :
2009
fDate :
6/1/2009 12:00:00 AM
Firstpage :
915
Lastpage :
925
Abstract :
This paper addresses the problems related to resistive opens and bridging faults that lie out of the most critical paths. These faults cannot be detected by traditional delay fault testing because the induced delay defects are not large enough to result in timing violations when the test rate is equal to the nominal operating frequency. In spite of this problem, resistive opens and bridgings should be detected because they may give rise to reliability problems. To detect them, we propose a testing method that is based on the propagation of pulses within the faulty circuit and that exploits the degraded capability of faulty paths to propagate pulses. The effectiveness of our method is analyzed at the transistor level and compared with the use of reduced clock periods to detect the same class of faults. Results show similar performance in the case of resistive opens and better performance in the case of bridgings. Moreover, the proposed approach is not affected by possible problems in the clock distribution.
Keywords :
CMOS logic circuits; fault simulation; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; transistor circuits; bridging faults; faulty circuit; pulse propagation; reduced clock period; resistive open; transistor level; Bridging faults; digital ICs´ testing; open faults; test generation; timing defects;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2009.2017080
Filename :
4957603
Link To Document :
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