• DocumentCode
    905238
  • Title

    The least complex parallel Massey-Omura multiplier and its LCA and VLSI designs

  • Author

    Shayan, Y.R. ; Le-Ngoc, T.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
  • Volume
    136
  • Issue
    6
  • fYear
    1989
  • fDate
    12/1/1989 12:00:00 AM
  • Firstpage
    345
  • Lastpage
    349
  • Abstract
    It is known that for m>or=4 there is more than one irreducible polynomial which generates a GF(2m) represented in normal basis. Therefore, a parallel Massey-Omura multiplier in GF(2m) has more than one structure for m>or=4. The number of these structures is equal to the number of irreducible polynomials which can generate that specific Galois field in a normal-basis representation. In this paper, as an illustrative example, the structure of GF(25) multipliers for different generator polynomials are compared. Based on this comparison, the least complex structure for this multiplier is introduced. The implementation of this structure using LCA (logic cell array) and VLSI (very large scale integration) technologies is given. Their complexities and propagation delays are compared.
  • Keywords
    CMOS integrated circuits; VLSI; digital arithmetic; logic arrays; logic design; multiplying circuits; parallel processing; polynomials; CMOS IC; Galois field; VLSI designs; complexities and propagation delays; generator polynomials; least complex structure; logic cell array; parallel Massey-Omura multiplier;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices and Systems, IEE Proceedings G
  • Publisher
    iet
  • ISSN
    0956-3768
  • Type

    jour

  • Filename
    216673