Title :
The Design of a Semi-Custom Integrated Circuit for the SLAC SLC Timing Control System
Author_Institution :
Stanford Linear Accelerator Center, Stanford, California, 94305
Abstract :
A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC´s experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given.
Keywords :
CAMAC; Control systems; Costs; Delay effects; Libraries; Packaging; Process design; Programmable logic arrays; Resistors; Timing;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.1985.4336797
