Sparcle: an evolutionary processor design for large-scale multiprocessors

Author

Agarwal, Anant ; Kubiatowicz, John ; Kranz, David ; Lim, Beng-Hong ; Yeung, Donald ; D´Souza, Godfrey ; Parkin, Mike

Author_Institution

Lab. for Comput. Sci., MIT, Cambridge, MA, USA

Volume

13

Issue

3

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

48

Lastpage

61

Abstract

The design of the Sparcle chip, which incorporates mechanisms required for massively parallel systems in a Sparc RISC core, is described. Coupled with a communications and memory management chip (CMMU) Sparcle allows a fast, 14-cycle context switch, an 8-cycle user-level message send, and fine-grain full/empty-bit synchronization. Sparcle´s fine-grain computation, memory latency tolerance, and efficient message interface are discussed. The implementation of Sparcle as a CPU for the Alewife machine is described.<>

Keywords

microprocessor chips; multiprocessing systems; reduced instruction set computing; Alewife machine; CMMU; Sparc RISC core; Sparcle chip; communications and memory management chip; fine-grain computation; massively parallel systems; memory latency tolerance; message interface; Communication switching; Delay; Large scale integration; Large-scale systems; Microprocessors; Process design; Reduced instruction set computing; Sun; Switches;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.216748

Filename

216748