Tradeoff literals against support for logic synthesis of LUT-based FPGAs

The paper deals with logic synthesis of lookup-table (LUT) based field-programmable gate arrays (FPGAs). Because each LUT can implement any k input Boolean function with the same area cost, the optimisation criterion of literal count, generally used in other multi-level logic synthesis methods, is not suitable for LUT-based technologies. Therefore a new logic optimisation criterion is proposed, which trades off literals against support. Based on this criterion, five logic operations in logic optimisation are analysed, and made to evaluate the circuit cost in accordance with the target technology. Using these techniques of logic optimisation, a good starting point for technology mapping of LUT-based FPGAs has been obtained. In the technology mapping phase, LUT-directed decomposition is applied. Experimental results indicate that synthesised circuits are much smaller and more routable than the circuits synthesised by other tools