Title :
Accurate simultaneous switching noise estimation including velocity-saturation effects
Author :
Vemuru, Srinivasa R
Author_Institution :
Dept. of Electr. Eng., City Univ. of New York, NY, USA
fDate :
5/1/1996 12:00:00 AM
Abstract :
Simultaneous switching noise (SSN) on power supply lines is caused by the large switching transient currents flowing through parasitic inductances at the chip-package-pin interface. A new expression to estimate SSN in CMOS circuits that includes the velocity saturation effects seen in the short-channel MOSFETs is derived. SPICE Level 3 simulation results show that the formula predicts the SSN more accurately as compared to existing approaches for submicron processes even at reduced supply voltages
Keywords :
CMOS integrated circuits; SPICE; driver circuits; integrated circuit noise; power system transients; CMOS circuits; SPICE Level 3 simulation; carrier velocity saturation; chip-package-pin interface; parasitic inductances; power supply lines; short-channel MOSFETs; simultaneous switching noise; submicron processes; switching transient currents; Circuit noise; Driver circuits; Inductance; Inverters; MOSFETs; Negative feedback; Power supplies; Predictive models; SPICE; Voltage;
Journal_Title :
Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on
