Noise computation in single chip packages

Author

Bathey, Kumaresh ; Swaminathan, Madhavan ; Smith, L.D. ; Cockerill, T.J.

Author_Institution

Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

Volume

19

Issue

2

fYear

1996

fDate

5/1/1996 12:00:00 AM

Firstpage

350

Lastpage

360

Abstract

This paper describes the computation of noise in single chip packages forming an integral part of a larger system. An analysis tool is discussed that integrates the details of chip, first level, and second level packages to form a network for simulation. The tool is useful in the computation of noise generated by single chip packages and allows for post-layout, pre-fabrication noise estimation. This paper provides details on the components of noise including resonance which is often over looked in most computations. Time domain measurements have been used to validate the noise analysis

Keywords

integrated circuit noise; integrated circuit packaging; first level packages; noise analysis; resonance; second level packages; simulation network; single chip packages; system analysis tool; time domain measurements; Circuit noise; Noise generators; Noise level; Noise measurement; Packaging; Resonance; Semiconductor device measurement; Time measurement; Voltage fluctuations; Working environment noise;

fLanguage

English

Journal_Title

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1070-9894

Type

jour

DOI

10.1109/96.496039

Filename

496039