Abstract :
A simple optimisation procedure for the design of travelling-wave amplifiers with two parallel gatelines and a common drain line is presented which utilises the full impedance matching potential involved. The parameters to be optimised for best broad-band performance of the amplifier are the characteristic impedances and, simultaneously, the line section lengths. The predicted performance of a design parallel distributed amplifier, employing eight typical 0.7 ¿m × 300 ¿m FETs, i.e. four for each of the two parallel gate-lines, shows 8.8 ± 0.5 dB gain over the frequency range 2¿16.5 GHz.
Keywords :
circuit CAD; microwave amplifiers; optimisation; solid-state microwave circuits; wideband amplifiers; 2 to 16.5 GHz; CAD; SHF; broad-band performance; characteristic impedances; common drain line; computer-aided design; impedance matching; line section lengths; optimisation procedure; parallel distributed amplifier; parallel-gate transmission lines; solid-state microwave circuits; travelling-wave amplifier;
