• DocumentCode
    909464
  • Title

    A transition sequence generator for RAM fault detection

  • Author

    Regener, E.

  • Author_Institution
    Dept. of Comput. Sci., Concordia Univ., Montreal, Que., Canada
  • Volume
    37
  • Issue
    3
  • fYear
    1988
  • fDate
    3/1/1988 12:00:00 AM
  • Firstpage
    362
  • Lastpage
    368
  • Abstract
    In verification of n-bit CMOS memories it is usual to supply a test address sequence having n2n transitions, one for each ordered pair of n-bit words which differ in a single bit. From an inductive definition of a sequence with these properties, a succession of algorithms yielding the logic circuit of a next-state generator for the sequence is developed. Proving these algorithms equivalent demonstrates the correctness of the circuit rigorously
  • Keywords
    CMOS integrated circuits; integrated circuit testing; integrated memory circuits; random-access storage; RAM fault detection; logic circuit; n-bit CMOS memories; next-state generator; ordered pair; test address sequence; transition sequence generator; Circuit faults; Circuit testing; Computer architecture; Fault detection; Fault tolerance; Fault tolerant systems; Logic circuits; Parallel processing; Random access memory; Read-write memory;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.2175
  • Filename
    2175
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=909464