A sublithographic antifuse structure for field-programmable gate array applications

Author

Chen, Kueing-Long ; Liu, David K Y ; Misium, George ; Gosney, W. Milton ; Wang, Shoue-Jen ; Camp, Janet ; Tigelaar, Howard

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

13

Issue

1

fYear

1992

Firstpage

53

Lastpage

55

Abstract

The authors demonstrate an antifuse structure with a cell area of 0.2*0.2 mu m/sup 2/ which is fabricated by using the vertical sidewall of a polysilicon interconnect layer and two-mask patterning and etching steps. The antifuse is constructed in such a way that its vertical dimension is determined by the thickness of the polysilicon layer, and its horizontal dimension is determined by two-mask patterning and etching steps. For a conventional contact-hole type of structure, a 0.2- mu m lithographic capability would be required to achieve the same antifuse cell size. It is also demonstrated that the time-dependent dielectric breakdown (TDDB) reliability of this sidewall antifuse is as good as that of a conventional planar contact-hole antifuse.<>

Keywords

logic arrays; reliability; 0.2 micron; FPGA; TDDB; antifuse cell size; antifuse structure; cell area; field-programmable gate array; horizontal dimension; reliability; sidewall antifuse; sublithographic antifuse size; time-dependent dielectric breakdown; vertical dimension; Breakdown voltage; Capacitance; Degradation; Dielectrics; Etching; Field programmable gate arrays; Low voltage; Semiconductor diodes; Senior members; Silicon;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.144949

Filename

144949