An experimental study of testing techniques for bridging faults in CMOS ICs

Author

Lanzoni, M. ; Favalli, M. ; Ambanelli, M. ; Olivo, P. ; Riccò, B.

Author_Institution

DEIS, Bologna Univ., Italy

Volume

28

Issue

6

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

686

Lastpage

690

Abstract

An experimental analysis of discrete Fourier transform (DFT) techniques used to detect the presence of faulty resistive paths throughout CMOS ICs is presented. Current monitoring, delay fault testing, and new design-for-testability (DFT) techniques are compared by means of a chip designed ad hoc that allows the presence of resistive bridgings within standard functional blocks to be simulated via hardware. The results suggest that specific DFT techniques offer considerable advantages over more conventional approaches

Keywords

CMOS integrated circuits; delays; design for testability; electron beam testing; fast Fourier transforms; fault location; integrated circuit testing; CMOS ICs; DFT techniques; I_DDQ test; bridging faults; current monitoring; delay fault testing; design-for-testability; discrete Fourier transform; faulty resistive paths; quiescent power supply current; resistive bridgings; testing techniques; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Hardware; Logic; Monitoring; Power supplies; Propagation delay; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.217984

Filename

217984