DocumentCode :
910144
Title :
X-compact: an efficient response compaction technique
Author :
Mitra, Subhasish ; Kim, Kee Sup
Author_Institution :
Intel Corp., Sacramento, CA, USA
Volume :
23
Issue :
3
fYear :
2004
fDate :
3/1/2004 12:00:00 AM
Firstpage :
421
Lastpage :
432
Abstract :
X-Compact is an X-tolerant test response compaction technique. It enables up to exponential reduction in the test response data volume and the number of pins required to collect test response from a chip. The compaction hardware requires negligible area, does not add any extra delay during normal operation, guarantees detection of defective chips even in the presence of unknown logic values (often referred to as X´s), and preserves diagnosis capabilities for most practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test-data volume, test-input/output pins and tester channels, and also to improve test quality.
Keywords :
circuit simulation; circuit testing; compaction; X-compact; X-tolerant test response compaction technique; chip testing; compaction hardware; current design; defective chip detection; exponential reduction; test flows; test response data volume; test-input pin; test-output pin; tester channels; unknown logic values; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Flip-flops; Hardware; Logic; Pins;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2004.823341
Filename :
1269864
Link To Document :
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