Title :
Extraction of two-node bridges from large industrial circuits
Author :
Zachariah, Sujit Thomas ; Chakravarty, Sreejit
Author_Institution :
Design Technol. Group, Intel India Dev. Center, Bangalore, India
fDate :
3/1/2004 12:00:00 AM
Abstract :
Enumeration and prioritization of highly probable bridges based on the circuit layout and manufacturing defect data is a key step in defect-based testing. Existing solutions either do not scale to large designs or compromise on the accuracy of the computation when applied to very large circuits. This paper presents a scalable and efficient methodology to accurately extract two-node bridges from very large circuits. To our knowledge, this is the first solution to be presented that can process such large industrial designs accurately. It also naturally addresses two important issues viz. through the cell routing and name propagation. Experimental results illustrating key features of the algorithm, including scalability and efficient memory usage, are presented.
Keywords :
bridge circuits; circuit layout; circuit testing; memory architecture; network routing; cell routing; circuit layout; defect-based testing; large industrial circuits; manufacturing defect data; memory usage; name propagation; scalability; two-node bridge extraction; very large circuits; Automatic testing; Bridge circuits; Circuit faults; Circuit testing; Content addressable storage; Data mining; Failure analysis; Fault diagnosis; Manufacturing industries; Routing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2004.823351