Title :
Synthesis of fully testable circuits from BDDs
Author :
Drechsler, Rolf ; Shi, Junhao ; Fey, Görschwin
Author_Institution :
Inst. of Comput. Sci., Univ. of Bremen, Germany
fDate :
3/1/2004 12:00:00 AM
Abstract :
We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique.
Keywords :
circuit layout; circuit testing; equivalent circuits; binary decision diagram; circuit synthesis; fully testable circuits; inverter; linear time mapping algorithm; netlist; path-delay fault model; stuck-at fault model; Binary decision diagrams; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Data structures; Inverters; Logic circuits; Logic design; Redundancy;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2004.823342
