DocumentCode :
910300
Title :
VLSI and WSI associative string processors for structured data processing
Author :
Lea, R.M.
Author_Institution :
Brunel University, Department of Electrical Engineering and Electronics, Uxbridge, UK
Volume :
133
Issue :
3
fYear :
1986
fDate :
6/1/1986 12:00:00 AM
Firstpage :
113
Lastpage :
122
Abstract :
A novel fine-grain parallel-processing microelectronic architecture is proposed as a cost-effective building-block for fifth-generation computer systems. Based on a fully programmable associative string processing computational structure, the architecture provides particularly flexible support and manipulation of abstract data structures over a wide range of information processing tasks. Moreover, the architecture is well suited to the technological constraints of VLSI chip and, especially, WSI device fabrication. The paper describes the ASP (associative string processor) architecture and its instruction set. The style of associative string processing is introduced with three algorithms, illustrating both relational and arithmetic operations. Current projects leading to VLSI ASP chips and WSI ASP devices are discussed and `ball-park¿ performance figures are given.
Keywords :
VLSI; microprocessor chips; parallel processing; VLSI; WSI; abstract data structures; arithmetic operations; associative string processors; fifth-generation computer systems; fine-grain parallel-processing microelectronic architecture; instruction set; structured data processing;
fLanguage :
English
Journal_Title :
Solid-State and Electron Devices, IEE Proceedings I
Publisher :
iet
ISSN :
0143-7100
Type :
jour
DOI :
10.1049/ip-i-1.1986.0023
Filename :
4644157
Link To Document :
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