• DocumentCode
    910847
  • Title

    A general-purpose two-dimensional process simulator-OPUS for arbitrary structures

  • Author

    Nishi, Kenji ; Sakamoto, Kouichi ; Kuroda, Shigeki ; Ueda, Jun ; Miyoshi, Tatsurou ; Ushio, Shintaro

  • Author_Institution
    Oki Electr. Co. Ltd., Tokyo, Japan
  • Volume
    8
  • Issue
    1
  • fYear
    1989
  • fDate
    1/1/1989 12:00:00 AM
  • Firstpage
    23
  • Lastpage
    32
  • Abstract
    A general-purpose two-dimensional process simulator OPUS (Oki Process simulator for ULSI Structures) for arbitrary structures is discussed. By separating a preprocessor from a main processor, OPUS can simulate any kind of impurity or material with up to eight impurities and ten materials. OPUS utilizes a finite-difference method for diffusion analysis without any coordinate transformation. In order to minimize errors due to discretization around the curved boundaries, OPUS has introduced two kinds of boundaries. The first is true boundaries by strings. The other is quasi-boundaries formed through simplifying but retaining the shape of true boundaries as long as possible. The quasi-boundaries and resulting dummy cells are used for discretization of the diffusion equation. General features of OPUS are first introduced with special emphasis on dummy cells. Errors caused by dummy cells are discussed. The capacity of OPUS is then demonstrated through application to a trench process and to a full MOS process with a sidewall
  • Keywords
    MOS integrated circuits; VLSI; digital simulation; electronic engineering computing; integrated circuit technology; IC fabrication; MOS process; Oki Process simulator; ULSI Structures; VLSI; arbitrary structures; diffusion analysis; diffusion equation discretisation; dummy cells; finite-difference method; impurity simulation; quasi-boundaries; trench process; true boundaries; two-dimensional process simulator; Analytical models; Equations; Finite difference methods; Finite element methods; Impurities; Oxidation; Shape; Two dimensional displays; Ultra large scale integration; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.21815
  • Filename
    21815