Title :
MOTA: a MOSFET timing simulator
Author :
Jou, S.-J. ; Jen, C.-W. ; Shen, W.-Z. ; Lee, C.-L.
Author_Institution :
National Chiao Tung University, Institute of Electronics, Hsinchu, Republic of China
fDate :
10/1/1986 12:00:00 AM
Abstract :
MOTA: a new NMOS and CMOS timing simulator, is presented. Basically, it employs a one sweep nonlinear Gauss-Seidal relaxation technique to decouple node equations, and this results in a linear performance on the computation time over the number of the gates of the circuit. It has three distinct features: (a) it provides a `SUBCIRCUIT¿ capability to simulate tightly-coupled circuit blocks. This solves the inaccuracy and the instability problems which are usually encountered in existing timing simulators, (b) it employs a physical table model for MOS devices with only 250 storage points, and (c) it utilises a simple variable time step control scheme and internal and external bypass schemes to increase the simulation speed. The run examples show that it is approximately 60 times faster than SPICE2G-5 while giving comparable precision.
Keywords :
CMOS integrated circuits; circuit CAD; field effect integrated circuits; integrated circuit technology; CAD; CMOS; Gauss-Seidal relaxation technique; MOS devices; MOSFET timing simulator; MOTA; NMOS; computer-aided design; monolithic IC; one sweep nonlinear method; physical table model; subcircuit capability; tightly-coupled circuit blocks; variable time step control scheme;
Journal_Title :
Solid-State and Electron Devices, IEE Proceedings I
DOI :
10.1049/ip-i-1.1986.0041