Analysis of distributed resistance effects in MOS transistors

Author

Horan, John ; Lyden, Colin ; Mathewson, Alan ; Cahill, Ciaran G. ; Lane, W.A.

Author_Institution

Analog Devices BV, Limerick, Ireland

Volume

8

Issue

1

fYear

1989

fDate

1/1/1989 12:00:00 AM

Firstpage

41

Lastpage

45

Abstract

A method of modeling the distributed source and drain resistance effects in MOS transistors is discussed. Simulations performed using this technique are validated by comparisons with purpose-built structures. The method is then used to examine a problem which arises with the use of a high-temperature interconnect in three-dimensional silicon-on-insulator technologies. The results show how the resistivity of the interconnect affects the performance of the substrate devices of this technology, and the benefits achievable through further development of the existing interconnect technologies are outlined. Finally, the procedure is used to examine the effect of reduced contact size on standard MOS devices, and results wh1ich give general guidelines to the extent of the effect are presented

Keywords

MOS integrated circuits; electric resistance; electronic engineering computing; insulated gate field effect transistors; semiconductor device models; 3D SOI technologies; DMOS; MOS transistors; current flow; distributed resistance effects; drain resistance; high-temperature interconnect; modeling; reduced contact size; simulation strategy; source resistance; standard MOS devices; CMOS technology; Conductivity; Integrated circuit interconnections; Integrated circuit technology; MOS devices; MOSFETs; Silicides; Silicon on insulator technology; Temperature; Thermal stresses;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.21817

Filename

21817