• DocumentCode
    911054
  • Title

    The FASTBUS Intersegment Processor (FIP)

  • Author

    Charpentier, Ph ; Goujon, G. ; Gros, M. ; Mur, M. ; Paul, B.

  • Author_Institution
    DPhPE, CEN Saclay 91191 GIF-SUR-YVETTE Cedex (France)
  • Volume
    34
  • Issue
    1
  • fYear
    1987
  • Firstpage
    137
  • Lastpage
    141
  • Abstract
    The Fastbus Intersegment Processor (FIP) is a Fastbus [1] processor based on a MOTOROLA MC68020 [2] microprocessor system. It will be used in several detectors of the Delphi LEP experiment at CERN. Its architecture is oriented towards cellular multi-layered acquisition systems, where it provides data collection, processing and buffering at a particular level, as well as control and synchronisation from one level to the next. The Fastbus architecture, Fastbus interfaces, and the application foreseen for the Delphi TPC are covered in detail in the paper.
  • Keywords
    Backplanes; Central Processing Unit; Communication system control; Control systems; Detectors; Fastbus; Integrated circuit interconnections; Master-slave; Microprocessors; Read-write memory;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.1987.4337317
  • Filename
    4337317
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=911054