DocumentCode :
911118
Title :
Techniques for area estimation of VLSI layouts
Author :
Kurdahi, Fadi J. ; Parker, Alice C.
Author_Institution :
Dept. of Electr. Eng., California Univ., Irvine, CA, USA
Volume :
8
Issue :
1
fYear :
1989
fDate :
1/1/1989 12:00:00 AM
Firstpage :
81
Lastpage :
92
Abstract :
The standard cell design style is investigated. Two probabilistic models are presented. The first model estimates the wiring space requirements in the routing channels between the cell rows. The second model estimates the number of feedthroughs that must be inserted in the cell rows to interconnect cells placed several rows apart. These models were implemented in the standard cell area estimation program PLEST (PLotting ESTimator). PLEST was used to estimate the areas of a set of 12 standard cell chips. In all cases, the estimates were accurate to within 10% of the actual areas. PLEST´s estimation of a chip layout area takes only a few seconds to produce, as compared with more than 10 h to generate the chip layout itself using an industrial layout system
Keywords :
VLSI; application specific integrated circuits; circuit layout CAD; digital integrated circuits; probability; ASIC; CAD; PLEST; VLSI layouts; area estimation; digital IC; estimation program; probabilistic models; routing channels; software package; standard cell design; wiring space requirements; Circuit synthesis; Compaction; Councils; Digital integrated circuits; Integrated circuit interconnections; Logic design; Routing; State estimation; Very large scale integration; Wiring;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.21821
Filename :
21821
Link To Document :
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