Experimental evaluation of testability measures for test generation (logic circuits)

Author

Chandra, Susheel J. ; Patel, Janak H.

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

Volume

8

Issue

1

fYear

1989

fDate

1/1/1989 12:00:00 AM

Firstpage

93

Lastpage

97

Abstract

The results of an extensive study of five existing testability measures when used to aid heuristics for automatic test pattern generation algorithms are presented. Each measure was evaluated using over 60000 faults in circuits of varying size and complexity. The performance of these measures was rated using several different criteria. Based on these results the performance of a composite test generation strategy that uses multiple guidance heuristics was evaluated. The results indicate that this strategy not only provides better fault coverage but also reduces the average time taken to generate a test or determine that a given fault is undetectable

Keywords

automatic testing; fault location; logic testing; automatic test pattern generation algorithms; composite test generation strategy; logic circuits; multiple guidance heuristics; testability measures; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Costs; Logic circuits; Logic testing; Size measurement; Test pattern generators; Velocity measurement;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.21822

Filename

21822