Modeling of gate oxide shorts in MOS transistors

A unified approach is proposed for modeling gate oxide shorts in MOS transistors using lumped-element models. These models take into account the possible structure of gate oxide short and the resulting changes that affect the I-V characteristics of MOS transistors. They can be used with the circuit simulator to predict the performance degradation of the VLSI circuit with gate oxide shorts. Demonstrated examples of models show close agreement with the experimental data