DocumentCode :
911301
Title :
A quadrisection-based combined place and route scheme for standard cells
Author :
Suaris, Peter Ramyalal ; Kedem, Gershon
Author_Institution :
Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
Volume :
8
Issue :
3
fYear :
1989
fDate :
3/1/1989 12:00:00 AM
Firstpage :
234
Lastpage :
244
Abstract :
A description is given of a placement technique based on hypergraph quadrisection. The authors have developed a standard cell placement procedure based on recursively dividing the netlist into four parts, while minimizing the division cost. They have combined two ideas for placement. One is the extension of the min-cut bisection algorithm to handle quadrisection. The second idea is the simultaneous calculation of min-cut quadrisection and hierarchical global routing. The implementation details are discussed. The results show the implementation to be competitive with simulated annealing
Keywords :
cellular arrays; circuit layout CAD; integrated logic circuits; logic CAD; division cost; hierarchical global routing; hypergraph quadrisection; min-cut bisection algorithm; netlist; place; placement technique; route; simulated annealing; standard cells; Circuit simulation; Costs; Integrated circuit interconnections; Microelectronics; Partitioning algorithms; Routing; Simulated annealing; Standards development; Very large scale integration; Wire;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.21843
Filename :
21843
Link To Document :
بازگشت