Title :
Multiple stuck-open fault detection in CMOS logic circuits
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fDate :
4/1/1988 12:00:00 AM
Abstract :
It is shown that a test set based on two-pattern tests, which are designed to detect single stuck-open faults, can be found that detects all multiple stuck-open faults inside any CMOS gate in the circuit. The concept is extended to three-pattern tests, which are obtained for every single stuck-open fault at the checkpoints. If a certain condition is satisfied, then it can be shown that the resulting test set can detect any multiple stuck-open fault in the circuit. Even when this condition is not fully met, a very large percentage of the multiple stuck-open faults can still be guaranteed to be detected. For the special case of fan-out-free CMOS circuits, it is shown that a single stuck-open fault test set based on two-pattern tests can always be found that has 100% multiple stuck-open fault coverage. This test can also be guaranteed to be robust in the presence of arbitrary delays
Keywords :
CMOS integrated circuits; integrated logic circuits; logic circuits; logic testing; CMOS logic circuits; multiple stuck-open fault detection; two-pattern tests; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Monitoring; Semiconductor device modeling; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
