Title :
Realizing fault-tolerant interconnection networks via chaining
Author :
Tzeng, Nian-feng ; Yew, Pen-chung ; Zhu, Chuan-qi
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, IN, USA
fDate :
4/1/1988 12:00:00 AM
Abstract :
A scheme applicable to a wide class of multistage interconnection networks to enhance their fault-tolerant capability is proposed. Multiple paths between each input-output pair of a network are created by connecting switching elements within the same stage. This scheme provides a network with alternative paths at every stage, requires a simple self-routing algorithm, and allows a network to become more robust as its size increases. An analysis is performed to obtain a quantitative measurement of the reliability improvement of the scheme
Keywords :
fault tolerant computing; multiprocessor interconnection networks; chaining; fault-tolerant interconnection networks; multistage interconnection networks; quantitative measurement; reliability improvement; self-routing algorithm; switching elements; Fault tolerance; Hardware; Joining processes; Multiprocessing systems; Multiprocessor interconnection networks; Performance analysis; Performance evaluation; Redundancy; Robustness; Routing;
Journal_Title :
Computers, IEEE Transactions on
