• DocumentCode
    912149
  • Title

    Automating Technology Relative Logic Synthesis and Module Selection

  • Author

    Thomas, Donald E. ; Leive, Gary W.

  • Author_Institution
    Department of Electrical Engineering, Carnegie-Mellon University, Pittsburgh, PA, USA
  • Volume
    2
  • Issue
    2
  • fYear
    1983
  • fDate
    4/1/1983 12:00:00 AM
  • Firstpage
    94
  • Lastpage
    105
  • Abstract
    This paper discusses a design aid which translates the data part of a functional level digital design into a logic level design through the specification of module set information. The constraint driven automatic methodology is discussed and results of using the design aid are presented. Predictors are developed to estimate the logic level design space, thus providing early feedback within the design process.
  • Keywords
    Automatic logic units; Computational modeling; Computer simulation; Digital systems; Hardware; Logic design; Logic testing; Space exploration; Space technology; Tellurium;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1983.1270025
  • Filename
    1270025