• DocumentCode
    912219
  • Title

    Resistance Extraction from Mask Layout Data

  • Author

    Horowitz, Mark ; Dutton, Robert W.

  • Author_Institution
    Department of Electrical Engineering, Stanford University, Palo Alto, CA, USA
  • Volume
    2
  • Issue
    3
  • fYear
    1983
  • fDate
    7/1/1983 12:00:00 AM
  • Firstpage
    145
  • Lastpage
    150
  • Abstract
    This paper presents a new algorithm to extract resistance values from an integrated circuit artwork description. Instead of trying to solve for the exact resistance values, heuristics are used to find an approximate solution. The algorithm first breaks the input polygons into simple pieces, and then finds the resistance through each piece. This procedure enables the extraction to be both fast and memory efficient. The heuristics used for splitting the polygons and calculating the pieces´ resistance are derived from rules of electrostatics, and yield answers that are within 10 percent of the exact resistance values. The operations needed to break complex polygons into simpler pieces are very similar to other geometric operations used in artwork analysis systems.
  • Keywords
    Chip scale packaging; Contact resistance; Data mining; Electric resistance; Electrical resistance measurement; Electrostatics; Integrated circuit yield; Parasitic capacitance; Resistors; Shape;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1983.1270032
  • Filename
    1270032