Title :
Single-Layer Routing for VLSI: Analysis and Algorithms
Author :
Marek-Sadowska, Malgorzata ; Tarng, Tom Tsan-Kuo
Author_Institution :
Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA, USA
fDate :
10/1/1983 12:00:00 AM
Abstract :
In this paper we present a discussion of planarity testing and detailed single-layer routing. A program which implements the proposed algorithms for routing nets inside an arbitrarily shaped region has been written and tested. The results from this program are shown as examples.
Keywords :
Algorithm design and analysis; Circuit testing; Complexity theory; Digital systems; Integrated circuit interconnections; Laboratories; Microelectronics; Routing; Topology; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1983.1270042
