Title :
Graph-Optimization Techniques for IC Layout and Compaction
Author :
Kedem, Gershon ; Watanabe, Hiroyuki
Author_Institution :
Computer Science Department, University of Rochester, Rochester, NY USA
fDate :
1/1/1984 12:00:00 AM
Abstract :
This paper describes a new approach for IC layout and compaction. The compaction problem is translated into a mixed integer-linear programming problem of a very special form. A graph-based optimization algorithm is used to solve the resulting problem. An experimental program that uses the above techniques is described. The program could be used either as an aid to hand layout or as the bottom part of an automatic layout generation program.
Keywords :
Application specific integrated circuits; Compaction; Digital circuits; Heuristic algorithms; Integrated circuit layout; Libraries; Logic circuits; Logic design; Minimization; Shape;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1984.1270052
