• DocumentCode
    912545
  • Title

    Characterizing the LSI Yield Equation from Wafer Test Data

  • Author

    Seth, Sharad C. ; Agrawal, Vishwani D.

  • Author_Institution
    Department of Computer Science, University of Nebraska, Lincoln, NE, USA
  • Volume
    3
  • Issue
    2
  • fYear
    1984
  • fDate
    4/1/1984 12:00:00 AM
  • Firstpage
    123
  • Lastpage
    126
  • Abstract
    The results of production test on LSI wafers are analyzed to determine the parameters of the yield equation. Recognizing that a physical defect on a chip can produce several logical faults, the number of faults per defect is assumed to be a random variable with Poisson distribution. The analysis provides a relationship between the yield of the tested fraction of the chip area and the cumulative fault coverage of test patterns. The parameters of the yield equation are estimated by fitting this relation to the measured yield versus fault coverage data.
  • Keywords
    Condition monitoring; Large scale integration; Logic testing; Pattern analysis; Pattern recognition; Poisson equations; Production; Random variables; Semiconductor device measurement; Yield estimation;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1984.1270065
  • Filename
    1270065