A Network Comparison Algorithm for Layout Verification of Integrated Circuits

An algorithm is presented which compares the actual topology of an integrated circuit derived from its layout with a user-supplied description of the intended nominal circuit at the transistor level. Devices and nets in both circuits may be named arbitrarily. Using information about device types and pin types to weight the nodes of the corresponding graphs, isomorphism is tested and the names of devices and nets are matched. Differences are isolated and result in an error report for layout correction. The implemented program NEtwork COMparison (NECOM) has proven to be particularly efficient for analog bipolar circuits. It represents an essential part of a recently developed complete mask artwork analysis system called ALAS.