• DocumentCode
    912570
  • Title

    PART: Programmable Array Testing Based on a Partitioning Algorithm

  • Author

    Somenzi, Fabio ; Gai, Silvano ; Mezzalama, Marco ; Prinetto, Paola

  • Author_Institution
    SGS ATES Componenti Elettronici S.p.A., Central R & D, Agrate Brianza (MI), Italy
  • Volume
    3
  • Issue
    2
  • fYear
    1984
  • fDate
    4/1/1984 12:00:00 AM
  • Firstpage
    142
  • Lastpage
    149
  • Abstract
    PART is a system for PLA testing and design verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment. To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information. PART aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage. This is achieved by means of an efficient partitioning algorithm together with powerful heuristics. Test minimality is ensured by a simple procedure. In the present paper these are discussed, experimental results are given and a comparison with competing strategies is made.
  • Keywords
    Design automation; Equations; Partitioning algorithms; Power generation; Programmable logic arrays; Research and development; Silicon; System testing; Test pattern generators; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1984.1270068
  • Filename
    1270068