DocumentCode :
912655
Title :
Module Placement Based on Resistive Network Optimization
Author :
Cheng, Chung-Kuan ; Kuh, Ernest S.
Author_Institution :
Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA, USA
Volume :
3
Issue :
3
fYear :
1984
fDate :
7/1/1984 12:00:00 AM
Firstpage :
218
Lastpage :
225
Abstract :
A new constructive placement and partitioning method based on resistive network optimization is proposed. The objective function used is the sum of the squared wire length. The method has the feature which includes fixed modules in the formulation. The overall algorithm comprises the following subprograms: optimization, scaling, relaxation, partitioning and assignment. The method is efficient because it takes advantage of net-list sparsity and has a complexity of O[n1.4 log n]. Another added special feature is that irregular-size modules within cell rows are allowed. Thus the method is particularly useful in standard-cell and gate-array designs. Experimental results on four 4K gate-array placements are illustrated, and they are far superior than manual placements.
Keywords :
Aerospace electronics; Computational efficiency; Constraint optimization; Helium; Microelectronics; Nonlinear equations; Optimization methods; Partitioning algorithms; Sparse matrices; Wire;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1984.1270078
Filename :
1270078
Link To Document :
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