A Pattern Recognition Based Method for IC Failure Analysis

Random fluctuations which are inherent in the IC manufacturing process cause production yields to be significantly less than 100 percent. Yield drop is caused by two types of faults, catastrophic and parametric. This paper deals with the diagnosis of parametric faults which occur during the manufacturing of IC´s and cause the yield to drop below some acceptable level. A statistical pattern recognition approach to IC failure analysis is developed in this paper. Identification of faults is based on the analysis of the joint probability density function of circuit performances. A number of alternative approaches to IC failure analysis are developed and their efficiency is discussed. Also a complete statistical pattern recognition system with learning capability is proposed and all the stages of its development are discussed. An efficient method for fault simulation which is based upon statistical process simulation is proposed. The performance of the algorithms proposed in this paper has been successfully verified for data collected from commercial fabrication processes and from computer simulation.