Parametric investigation of latch-up sensitivity in 1.25 μm CMOS technology

The dependence of latch-up sensitivity in 1.25 μm p-well, CMOS devices on layout parameters, backside contacts, and thickness of epitaxial layers has been investigated by analysis and testing using a specially designed test chip. Retrograde wells and small source-to-substrate/well contact spacings play a critical role in suppressing latch-up, especially in non-epitaxial devices, by reducing the gains of vertical transistors. The backside contact directs high currents to the n⁺ source without developing large IR drops underneath the p⁺ source, thereby increasing the holding current. The epitaxial layer devices exhibit the holding voltages substantially higher than the ones for the non-epitaxial devices. Analyses and measurements have shown that the vertical transistors are in the-active mode at latch-up in the epitaxial devices in contrast with the saturation mode in the non-epitaxial devices. There exists an optimum epitaxial layer thickness, at which the holding voltage is a maximum. The optimum spacing is primarily determined by the n⁺ to p⁺ source spacing.