Propagation Delay Measurements from a Timing Sampler Intended for Use in Space

This paper describes a 3-¿m CMOS timing sampler which is a test circuit designied inito the JPL CRRES chip to be flown on the Coombined Release and Radiation Effects Satellite (CRRES). The timing sampler consists of 64 inverter-pair stages with sampling latches anid decoder circuitry. The sampler is used to measure inverter-pair propagation delays, which are nominally 2.5 nanoseconds, with a resolutioni of 100 picoseconds. A simple model was developed to explain the radiation-induced inverter-pair delay shifts in terms of radiation-induced MOSFET-threshold voltage shifts and effective nodal capacitances. The magnitude of the shift in pair delay with radiation was estimated at the point where the n-MOSFET threshold voltage became zero. For a 0.7-volt threshold shift, the pairdelay increased from its preradiation value by 360 picoseconds for a rising step iniput and decreased by 190 picoseconds for a falling step input.