Title :
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
Author_Institution :
Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA, USA
fDate :
7/1/1985 12:00:00 AM
Abstract :
In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.
Keywords :
Application specific integrated circuits; Design automation; Design optimization; Integrated circuit modeling; Lithography; Pulp manufacturing; Semiconductor device modeling; Solid modeling; Very large scale integration; Virtual manufacturing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1985.1270112
