DocumentCode :
913955
Title :
Design Analysis of GaAs Direct Coupled Field Effect Transistor Logic
Author :
Peczalski, Andrzej ; Shur, Michael S. ; Hyun, Choong H. ; Lee, Kang W. ; Vu, Tho Truong
Author_Institution :
Honeywell Inc., System and Research Center, Minneapolis, MN, USA
Volume :
5
Issue :
2
fYear :
1986
fDate :
4/1/1986 12:00:00 AM
Firstpage :
266
Lastpage :
273
Abstract :
Parameters of a DCFL inverter, such as propagation delay, inverter gain, switching voltage, output voltage levels and noise margins, are related (in an analytical form) to the parameters of the switching transistor and load transistor, such as the load saturation current, the switching transistor threshold voltage, the load and switching transistor output conductances, etc., and to the gate fan-in and fan-out. The results demonstrate tradeoffs between the noise margins, propagation delay and power consumption and are in reasonable agreement with experimental data for GaAs self-aligned inverters and with the results of circuit simulation of DCFL inverters and ring oscillators.
Keywords :
Circuit noise; Circuit simulation; Energy consumption; FETs; Gallium arsenide; Inverters; Logic design; Noise level; Propagation delay; Threshold voltage;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1986.1270195
Filename :
1270195
Link To Document :
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