Title :
Asynchronous binary restoring divider array
Author_Institution :
Monash University, Department of Electrical Engineering, Melbourne, Australia
Abstract :
The timing of an asynchronous restoring division array is investigated, and it is shown that this array is substantially faster than the synchronous array and marginally faster than the asynchronous nonrestoring division array.
Keywords :
carry logic; digital arithmetic; dividing circuits; asynchronous restoring division array; carry delay; carry logic; complement carry adders; dividing circuits;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19710367
