• DocumentCode
    914030
  • Title

    FINDER: A CAD System-Based Electron Beam Tester for Fault Diagnosis of VLSI Circuits

  • Author

    Kuji, Norio ; Tamama, Teruo ; Nagatani, Mitsoyoshi

  • Author_Institution
    Atsugi Electrical Communication Laboratory, NTT, Atsugi-shi, Kanagawa, Japan
  • Volume
    5
  • Issue
    2
  • fYear
    1986
  • fDate
    4/1/1986 12:00:00 AM
  • Firstpage
    313
  • Lastpage
    319
  • Abstract
    A new electron beam tester, "FINDER" (Fault Identification system for LSI circuits with a Noncontacting Database-oriented Electron beam testeR), has been developed. This tester can automatically pinpoint faulty gates in logic VLSI circuits. It consists of a Scanning Electron Microscope (SEM) and an LSI Computer-Aided Design (CAD) system in a host computer. A logic-state image is observed from the surface of an LSI circuit being tested with the SEM. In addition, corresponding interconnection patterns superimposed with simulated logic states are obtained from the CAD system. Both images are matched automatically in the host computer, and the observed logic state for every interconnection pattern is then checked. Faulty gates can be pinpointed by tracing nodes with incorrect logic states on a logic circuits.
  • Keywords
    Circuit faults; Circuit testing; Electron beams; Fault diagnosis; Large scale integration; Logic circuits; Logic testing; Scanning electron microscopy; System testing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1986.1270201
  • Filename
    1270201