Title :
VLSI Simulation and Data Abstractions
Author :
Katzenelson, Jacob ; Weitz, Eliezer
Author_Institution :
Department of Electrical Engineering, Technion-Israel Institute of Technology, Haifa, Israel
fDate :
7/1/1986 12:00:00 AM
Abstract :
Multilevel simulation is a technique for specifying and testing VLSI chip designs. This paper compares three methods of implementing such simulators: (a) Programming using a high level language that does not have data abstraction, e.g., Pascal. (b) Programming with procedure oriented data abstractions as in Simula [3] or CLU [4]. (c) Programming with enhanced C´s (EC) [2] data abstractions that are macro oriented. LIST -- a generator for simulation programs based on the data abstraction technique is described briefly. It is concluded that the use of data abstractions offers structure, hierarchy and simplicity. The use of EC has the additional advantage of run-time efficiency.
Keywords :
Chip scale packaging; Computational modeling; Hardware; Jacobian matrices; Logic design; Logic devices; Process design; Runtime; Testing; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1986.1270206