Concurrency and Communication in Hardware Simulators

This paper describes models for concurrency and interpartition communication in a hardware logic simulator implemented using multiprocessors. Software simulation data from production VLSI chips were analyzed in the context of a multiprocessor environment to obtain experimental values for concurrency and communication. The VLSI chips were randomly partitioned in the above experiments. The concurrency observed is significantly lower than the maximum achievable theoretically. This effect was more pronounced for circuits with lower activity. The effect of different simulators (unit and multiple delay), on concurrency and communication, is explained. Finally, a partitioning heuristic whose objective is to enhance concurrency and minimize communication is proposed. It makes use of the circuit topology and the delay information in a simulation database.