Title :
A Ranking Algorithm for MOS Circuit Layouts
Author :
Neff, C. Andrew ; Nair, Ravi
Author_Institution :
IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
fDate :
1/1/1987 12:00:00 AM
Abstract :
In the synthesis of digital circuits, one encounters the problem of identifying blocks which have been designed, so that there is no replication in the expensive effort of generating the physical layout of these blocks. We present a model for the synthesis of combinational logic into complex MOS circuits and present a ranking and unranking procedure to characterize the layout of each complex MOS circuit.
Keywords :
CMOS technology; Circuit synthesis; Digital circuits; Helium; Integrated circuit synthesis; Inverters; Logic circuits; Logic design; Physics computing; Programmable logic arrays;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1987.1270241
