• DocumentCode
    914477
  • Title

    Block-Level Hardware Logic Simulation Machine

  • Author

    Takasaki, Shigeru ; Sasaki, Tohru ; Nomizu, Nobuyoshi ; Koike, Nobhuiko ; Ohmori, Kenji

  • Author_Institution
    NEC Corporation, Fuchu City, Tokyo, Japan
  • Volume
    6
  • Issue
    1
  • fYear
    1987
  • fDate
    1/1/1987 12:00:00 AM
  • Firstpage
    46
  • Lastpage
    54
  • Abstract
    This paper describes a block-level hardware logic simulation machine. This is called a Hardware Logic Simulator (HAL). This paper first shows a block-level simulation method. Then, it overviews HAL hardware and software system configurations, and the simulation mechanism, and it estimates system performance. Finally, it discusses system applications and results. The paper also indicates that HAL has been successfully used.
  • Keywords
    Special-purpose hardware; block-level simulation; logic simulation; parallel processing; pipeline processing; Application software; Computational modeling; Design methodology; Digital systems; Discrete event simulation; Hardware; Large scale integration; Logic; Manufacturing; Prototypes;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1987.1270245
  • Filename
    1270245
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=914477