DocumentCode :
914617
Title :
A Simple Yet Effective Technique for Global Wiring
Author :
Nair, Ravi
Author_Institution :
IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
Volume :
6
Issue :
2
fYear :
1987
fDate :
3/1/1987 12:00:00 AM
Firstpage :
165
Lastpage :
172
Abstract :
A simple algorithm to perform global wiring is described. Repeated iterations of the algorithm tend to improve the quality of wiring by rerouting around congested areas. Various parameters can be set to give preference to short routes or to reduce the time taken by the algorithm. The algorithm has been tried out for several master-slice chips containing up to 3500 cells with good results. The technique is easily extended to standard cell chip design. An implementation for global wiring of a structured custom chip design style is described along with results. The technique is adaptable to higher level packaging such as chips on modules or modules on a board.
Keywords :
Channel capacity; Chip scale packaging; Design automation; Guidelines; Integrated circuit interconnections; Logic circuits; Metallization; Topology; Wires; Wiring;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1987.1270260
Filename :
1270260
Link To Document :
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