DocumentCode
914790
Title
FFT butterfly network design for easy testing
Author
Wu, Cheng-Wen ; Chang, Chen-Ti
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
40
Issue
2
fYear
1993
fDate
2/1/1993 12:00:00 AM
Firstpage
110
Lastpage
115
Abstract
The authors consider offline testing and easily testable design of butterfly networks for fast Fourier transform. The butterfly networks are shown to be testable with 32 patterns using a design-for-testability technique based on the M-testability conditions. The functional-level cell-fault model is assumed, and the fault coverage for combinational single cell faults is 100%. A higher-level fault model-the module-fault model-is also discussed. A novel input-assignment technique based on the functional bijectivity property of the butterfly modules is presented for discovering faults other than cell faults (e.g., interconnection faults)
Keywords
design for testability; fast Fourier transforms; fault location; logic design; logic testing; multiprocessor interconnection networks; signal processing; FFT butterfly network design; M-testability conditions; combinational single cell faults; design-for-testability; fast Fourier transform; fault coverage; functional bijectivity property; functional-level cell-fault model; input-assignment technique; interconnection faults; module-fault model; offline testing; testable design; Built-in self-test; Circuit faults; Fast Fourier transforms; Fault detection; Hardware; Logic arrays; Logic design; Logic testing; Tellurium; Throughput;
fLanguage
English
Journal_Title
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1057-7130
Type
jour
DOI
10.1109/82.219841
Filename
219841
Link To Document