Title :
Compaction-Based Custom LSI Layout Design Method
Author :
Ishikawa, Masaki ; Matsuda, Tsuneo ; Yoshimura, Takeshi ; Goto, Satoshi
Author_Institution :
C & C Systems Research Laboratories, NEC Corporation, Kawasaki, Japan
fDate :
5/1/1987 12:00:00 AM
Abstract :
This paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1.2-1.4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design.
Keywords :
Chip scale packaging; Compaction; Design automation; Design methodology; Laboratories; Large scale integration; Routing; Shape; Very large scale integration; Wiring;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1987.1270282
